The present invention relates to a pass transistor type selector circuit and a digital logic circuit using the same.
As shown in FIG. 8 by way of example, a pass transistor type selector circuit can be formed by interconnecting the drain electrodes D of a pair of signal selecting transistors 1 and 2 (pass transistors). Each of the pass transistors is usually composed of an nMOS transistor which operates at a high speed.
When a pair of input signals are selectively applied to the source electrodes S of the transistors 1 and 2 and a pair of control signals are selectively applied to the gate electrodes G of those transistors, this selector circuit functions as a two-input exclusive-OR circuit. Refer to, for example, N. Weste and K. Eshraghian, "Principles of CMOS VLSI Design", pp. 172-175, Addison-Wesley, 1985.
The pass transistor type selector circuit can be composed of a relatively small number of circuit elements. Accordingly, this type of selector circuit is particularly suitable for assembling a digital logic circuit having a desired high speed, by using the technology of VLSI (very-large-scale integration).
FIG. 9a shows the waveforms of the pair of control signals Z and Z. The first control signal Z is applied to the gate electrode G of the first transistor 1, the level of which is kept high during the period indicating logic "1" and is kept low during the period indicating logic "0". The second control signal Z which is a negative signal (negation) having a opposite phase to the first control signal Z is applied to the gate electrode G of the transistor 2. The level of this signal is kept low while the level of the first signal Z is kept high and is kept high while the level of the first signal Z is kept low.
In case of the above-mentioned conventional circuit, it is difficult to avoid such a phenomenon that both of the transistors 1 and 2 become conductive simultaneously during a short period T, because both of the control signals Z and Z tend to exceed a fixed threshold level in the process of turning over of those signals. If such a phenomenon once occurred, the input signals applied to the respective source electrodes S of the transistors 1 and 2 pass through those transistors and collide with each other on the side of the drain electrodes D (output terminal). This collision causes an undesirable delay of circuit stabilization which brings about some obstruction of high-speed operation.
Similar problem also arises in case that a certain control signal for one of the pair of pass transistors is inverted by an inverter to use as a control signal for the other transistor. In this case, as a result that the timing of level change or phase change of the latter signal is delayed by the delay time originated from the characteristics of the inverter, there occurs an undesirable short period in which both of the pair of pass transistors become conductive simultaneously.